(1) Field of the Invention
This invention relates to semiconductor integrated circuit devices, and is directed to a method of forming small (subquarter-micrometer) closely spaced contacts for electrical interconnections on Ultra Large Scale Integration (ULSI) circuits. More specifically, the method uses a carbon doped hard mask to achieve a high density of small contacts with improved silicon oxide etch rates and improved profiles in the contact holes.
(2) Description of the Prior Art
In recent years, the integrated circuit density on the semiconductor substrate has dramatically increased. This increase in density has resulted from down scaling of the individual devices built in and on the substrate and the interconnecting patterned electrical conducting layers that are used to wire up the devices. Future requirements for even greater increases in packing density is putting additional demand on the semiconductor technologies, such as improved resolution in the photolithography and improved plasma etching techniques.
One processing area limiting the packing density is the fabrication of reliable closely spaced small contacts or via holes in the interlevel dielectric (ILD) layer over the patterned electrical conducting polysilicon or polycide (polysilicon/silicide) layers used to interconnect the discrete devices on the semiconductor substrate. When the contact hole image size is less than 0.25 micrometers (um) it is necessary to use much shorter wavelength ultraviolet (UV) light (for example, having 193 nanometer wavelengths) to expose the latent images in the photoresist layer that is then developed and used as the etch mask for the contact hole. This necessitates using an exposure tool having a large numerical aperture (NA) which with a much shallower depth of focus (DOF). As a result the next generation of process technology will require much thinner photoresist layers (e.g. as thin as 0.76 um) to achieve the required high resolution. Unfortunately, the interlevel dielectric layers (ILD) must remain reasonably thick to minimize the ILD capacitance, and hence the RC circuit delays. This results in aspect ratios for these small contact holes (depth/width) which can be quite large. Therefore it is becoming increasingly difficult to etch the deep contact hole without eroding away the relatively thin photoresist mask when the contact or via hole are etched.
One solution to this problem is to include a polysilicon hard mask under the thin photoresist mask to prevent punch through in the ILD layer (insulating layer). However, when a photoresist mask/polysilicon hard mask is used the plasma etching usually results in a non-volatile residue buildup on the sidewalls of the contact hole. For example, Kuo et al., in U.S. Pat. No. 5,563,098 teaches a method for making buried contacts in a substrate using a polysilicon hard mask. The polymer buildup that usually forms on the sidewall in the opening of a polysilicon layer is first removed with the photoresist mask by oxygen plasma ashing prior to implanting the contact. Another method for making buried contacts structure in which the contact is etched through polysilicon (hard mask) layer and a oxide is described by Kalnitsky in U.S. Pat. No. 5,410,174. In U.S. Pat. No. 5,201,993 by Langley a two step plasma etch process is described for patterning multi-structure of oxide/silicide/polysilicon with vertical profiles. Still another approach for improving the photoresist image fidelity is described by Hasimoto et al in U.S. Pat. No. 5,656,128 in which an amorphous carbon film is used as an anti-reflecting coating (ARC) under the photoresist mask. And in U.S. Pat. No. 4,975,144, by Yamazaki et al., a method is described for selectively removing an amorphous carbon film on a substrate after processing or on the surfaces in the plasma chamber using NF3 plasma etch. Another use of carbon implanted in a single crystal silicon substrate for making microstructures is described in "Synthesis of SiC Microstructures in Si Technology by High Dose Carbon Implantation: Etch-Stop Properties" by C. Serre et al., J. Electrochem. Soc. Vol 144, No. Jun. 6, 1997 pages 2211-2215. None of the above methods addresses the need to minimize residue build during etching which is crucial to the formation of very small vertical walled contact or via holes.
Therefore, there is still a problem when using a polysilicon hard mask for etching very small closely spaced contact holes with or without the photoresist. Local loading effects and the redeposition of non-volatile inorganics, such as SiO.sub.x, can result in non-repeatable and unreliable contact openings. This is best depicted with reference to FIG. 1, which shows several closely spaced contacts 2 etched in a ILD layer. Shown are the contact openings 2 plasma etched in a ILD oxide layer 14 to a polysilicon layer 12 on substrate 10. During plasma etching the patterned photoresist layer 18 used as the etch mask can result in polymeric residue buildup 5 on the sidewalls of the contact holes 2. When a polysilicon hard mask 16 is include inorganic contamination can also build up as residue 5 on the sidewalls of the contact holes, such as SiO.sub.x. These residues build-up results in rough sidewalls, and reduce the contact hole width. The release of excessive oxygen during the ILD etching lower the oxide etch rates. These effects prevent the formation of metal plugs in the contact holes with repeatable and reliable low contact resistance.
Therefore, there is still a strong need in the semiconductor industry for a contact hole etch process that reduces the sidewall residue during etching and enhances the oxide etch to provide reliable closely spaced very small contact holes (less than 0.25 um) in insulating layer for ULSI circuits.